Standard Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM) devices are considered volatile memory devices because data stored therein is lost when power is lost. Nonvolatile memory devices are those that can retain data despite loss of power.
At present, there is a strong market for EEPROM (Electrically Erasable, Programmable Read Only Memory), and Flash EEPROM nonvolatile memory devices. These devices tend to be slow to write-, often having write times on the order of milliseconds, while read times range generally between one nanosecond and one microsecond. The great difference between read and write times, together with the block-erase character of Flash EEPROM, complicates design of some systems. CMOS SRAM or DRAM with battery backup power for data retention can provide symmetrical, fast, read and write times in nonvolatile memory but is expensive, requires presence of a battery, and limits system life or requires eventual battery replacement.
It is known that Ferroelectric Random Access Memory (FRAM) is a nonvolatile memory technology having potential for both read and write times below one microsecond. FRAM nonvolatile memory devices based on Lead Zirconium Titanate (PZT) ferroelectric storage capacitors as memory elements integrated with CMOS addressing, selection, and control logic are known in the art and are commercially available. PLZT is a Lanthanum-doped form of PZT wherein some of the lead is replaced with Lanthanum, for purposes of this patent the term PZT includes PLZT. It is known that PZT may additionally be doped with strontium and calcium to improve its ferroelectric dielectric properties. Ferroelectric storage capacitors having a Strontium Bismuth Tanatalate (SBT) dielectric are also known in the art. For purposes of this patent the term Ferroelectric Dielectric includes both PZT and SBT materials.
It is expected that FRAM devices having smaller device geometries and smaller ferroelectric storage capacitors than currently available devices will offer greater speed and storage density at lower cost. Producing such FRAM devices requires production of improved, uniform, high quality, ferroelectric storage capacitors integrated with CMOS addressing and control logic.
It is known that some prior FRAM devices incorporate ferroelectric storage capacitors that degrade with repeated operation, this is known as fatigue degradation. Some prior FRAM devices incorporate complex circuitry for overcoming fatigue degradation, thereby complicating the design of the device. It is expected that improved, high quality ferroelectric storage capacitors may also permit production of FRAM devices that do not suffer from fatigue degradation without need of complex circuitry.
Ferroelectric storage capacitors of FRAM devices have a bottom electrode interfacing with a ferroelectric layer, often PZT or SBT, that serves as the ferroelectric dielectric. The ferroelectric layer is typically deposited on top of the bottom electrode, and a top electrode is deposited on top of the ferroelectric layer. Each layer is masked and etched to define the size and location of each capacitor. A passivation layer is formed over the resulting capacitors. This layer is masked and etched to allow connection of each capacitor to other components of each memory cell and to other components, such as CMOS addressing, selection, and control logic of the integrated circuit.
A prior process for fabricating the ferroelectric dielectric of ferroelectric storage capacitors is described in U.S. Pat. No. 6,090,443, (the '443 patent) entitled “Multi-Layer approach for optimizing Ferroelectric Film Performance” and assigned to Ramtron International Corporation, Colorado Springs, Colo., the disclosure of which is incorporated herein by reference. This process involves the following steps, including a two-step Rapid Thermal Anneal (RTA), all performed after deposition of a bottom electrode layer:
Sputter deposition of a metallic bottom electrode layer.
Sputter deposition of a lead-rich PZT nucleation layer.
Sputter deposition of a bulk PZT layer.
Optional sputter deposition of a lead-rich PZT cap layer. The PZT nucleation, bulk, and cap layers can alternatively be deposited by a spin-on process, and are calcium and strontium doped.
Annealing the deposited PZT by RTA in argon atmosphere to form intermetallic phases at the bottom electrode interface at 625 C for 90 seconds, RTA being performed by an AG Heatpulse 410 RTA unit.
Annealing the deposited PZT by RTA in oxygen atmosphere to crystallize the PZT at 750 C for 20 seconds.
Depositing a top electrode layer.
Furnace annealing the resulting structure prior to testing at 650 C for one hour.
While the process of the '443 patent can produce PZT films improved over prior art, there was still room for improvement in PZT quality and process complexity.